1. Field
This disclosure relates generally to memories, and more specifically, to programming split gate bit cell.
2. Related Art
Split gate non-volatile memories (NVMs) including, for example, split gate flash devices, provide advantages over stacked-gated devices. Split gate flash cells exhibit reduced program disturb for memory cells that are unselected but are either on the selected row or, in the alternative, on the selected column. Normally, cells on the selected row or the selected column are the most likely to exhibit disturb effects regardless of the operation that is being performed on a selected cell. While split gate flash cells have substantially reduced the program disturb problem for cells on the selected rows or columns, the program disturb of erased bits on cells of unselected rows/unselected columns are the primary disturb mechanism. One of the reasons that these cells are susceptible in split gate designs is that the particular stress applied to unselected cells is applied for many more cycles than the stress that is applied to cells on a selected row/unselected column or an unselected row/selected column.